The present invention generally relates to a method for making a semiconductor integrated circuit easily testable. More particularly, the present invention relates to a method for inserting a test circuit into each of a plurality of functional blocks, of which a semiconductor integrated circuit will be made up and for which associated test data sets are prepared, so as to make the integrated circuit externally testable. The present invention also relates to a method for converting test data prepared for each single functional block into test data of the type making testable an integrated circuit to which a test circuit has been inserted.
In recent years, a multiplicity of functional blocks, each of which is pre-designed to execute its own intended function, are used as building blocks for a semiconductor integrated circuit to design the circuit more efficiently. Each of these functional blocks is sometimes provided with test data representing input and expected (output) values thereof to detect a fault through testing. Examples of the functional blocks include logic circuit blocks, memory circuit blocks and large-scale functional blocks such as IP (intellectual property), VC (virtual core) and core.
In testing a semiconductor integrated circuit consisting of these functional blocks using such test data, test circuits should be inserted into the integrated circuit to make each of these functional blocks externally testable. According to the conventional technique, however, descriptions of the routes associated with each of these functional blocks should be modified manually to insert the test circuit thereto.
Also, to make each functional block externally testable through the test circuit inserted, test data prepared for the functional block should be converted into test data applicable to testing the semiconductor integrated circuit. This test data conversion process is also performed manually according to the conventional technique.
However, as the size of a single functional block has been considerably increasing lately, the number of pins per logic block has also been rising by leaps and bounds to reach several hundreds, several thousands or more. Also, as the case may be, a single semiconductor integrated circuit is sometimes made up of a number of functional blocks as mentioned above. Accordingly, insertion of a test circuit involves the work of drawing up a netlist describing connection routes between the input and output pins of each functional block under test and associated external pins at gate level, for example. In addition, even if each functional block is provided with corresponding test data, that test data should be converted into test data adapted to test the semiconductor integrated circuit. As can be seen, if these processes of inserting the test circuit and converting the test data associated with each of these functional blocks are performed manually, then an enormous number of process steps have to be carried out. Thus, the designer is much more likely to commit numerous errors during such overly complicated manual operations.
A first object of the present invention is inserting test circuits non-manually to make a semiconductor integrated circuit made up of a plurality of functional blocks easily testable.
A second object of the present invention is converting test data prepared for each of the building functional blocks of a semiconductor integrated circuit into test data of the type making the functional blocks in the integrated circuit externally testable.
To achieve the first object, the present invention obtains pin combination information, representing to which input or output pin of a functional block each external pin should be connected, to update routing information contained in existent circuit information.
To achieve the second object, the present invention converts test data associated with each single functional block into test data of the type making the integrated circuit externally testable based on the pin combination information.
Specifically, a first exemplary inserting method according to the present invention is adapted to achieve the first object by inserting a test circuit into an integrated circuit, which is made up of a plurality of functional blocks interconnected, such that test data can be externally input to at least one of the functional blocks when the functional block is tested. The method includes the step of a) obtaining pin allocation information including input and output pin connection information for the at least one functional block under test. The input pin connection information represents which input pin of the functional block should be connected to each external test data input pin. The output pin connection information represents which output pin of the functional block should be connected to each external test data output pin. The method further includes the steps of: b) obtaining machine-readable pin combination information by analyzing the pin allocation information; and c) inserting a test data input circuit between the functional block under test and the external test data input pin or a test data output circuit between the functional block under test and the external test data output pin based on the pin combination information.
According to the first inserting method, pin allocation information, including input and output pin connection information, which represents which input or output pin of the functional block under test should be connected to each external test data input or output pin, is obtained manually or automatically. Then, the pin allocation information is analyzed to obtain machine-readable pin combination information. Thus, information about a testable integrated circuit, including the test circuit (i.e., the test data input or output circuit) applied to the functional block under test, can be obtained without actually designing the test circuit. That is to say, routing information for testing the functional block can be obtained without performing a great deal of modification work manually. As a result, the number of design process steps can be drastically cut down.
A second exemplary inserting method according to the present invention is adapted to achieve the first object by inserting a test circuit into an integrated circuit, which is made up of a plurality of functional blocks interconnected, such that test data can be externally input to at least one of the functional blocks when the functional block is tested. The method includes the step of a) preparing pin allocation information including input and output pin connection information for the at least one functional block under test. The input pin connection information represents which input pin of the functional block should be connected to each external test data input pin. The output pin connection information represents which output pin of the functional block should be connected to each external test data output pin. The method further includes the steps of: b) obtaining routing information by analyzing interconnection routes of the functional block based on information about the integrated circuit; c) obtaining machine-readable pin combination information by analyzing the pin allocation information; and d) inserting a test data input circuit and an input signal direction controller between the external test data input pin and the functional block under test based on the pin combination information. The test data input circuit is used for inputting test data through the external test data input pin to the input pin of the functional block under test in a test mode. The input signal direction controller is provided for enabling the external test data input pin, which functions as an output or bidirectional pin in a normal operation mode, to input the test data in the test mode. The method further includes the step of e) inserting a test data output circuit and an output signal direction controller between the functional block under test and the external test data output pin. The test data output circuit is used for outputting the test data to the external test data output pin through the output pin of the functional block under test in a test mode based on the pin combination information. The output signal direction controller is provided for enabling the external test data output pin, which functions as an input or bidirectional pin in a normal operation mode, to output the test data in the test mode. The method further includes the step of f) updating the routing information based on how the test data input or output circuit inserted is connected and outputting the updated routing information as testable integrated circuit information.
According to the second inserting method, only by defining (or describing) pin allocation information including input and output pin connection information, which represents which input or output pin of the functional block under test should be connected to each external test data input or output pin, the designer can obtain information about a testable integrated circuit, including the test circuit (i.e., the test data input or output circuit) applied to the functional block under test, without actually designing the test circuit. In addition, even if the external test data input pin functions as an output pin in the normal operation mode, the input pin can be used as a bidirectional pin by inserting the input signal direction controller thereto. Similarly, even if the external test data output pin functions as an input pin in the normal operation mode, the output pin can also be used as a bidirectional pin by inserting the output signal direction controller thereto. Thus, the inventive method is easily adaptable to an automated design process.
In one embodiment of the present invention, the step a) preferably includes obtaining partitioning information for classifying the input or output pin connection information into a plurality of groups. The step d) preferably includes inserting the test data input circuit into each said group based on the partitioning information. And the step e) preferably includes inserting the test data output circuit into each said group based on the partitioning information. In such an embodiment, the test circuit itself can be laid out for each of the groups partitioned, thus improving the efficiency of a layout design process.
In another embodiment, the step a) preferably includes obtaining signal shaping buffer information indicating whether or not a signal shaping buffer should be added to the test data input or output circuit to shape a waveform of a signal that has been rounded during the propagation thereof. The step d) preferably includes inserting the signal shaping buffer into the test data input circuit based on the signal shaping buffer information. And the step e) preferably includes inserting the signal shaping buffer into the test data output circuit based on the signal shaping buffer information. In such an embodiment, a signal shaping buffer can be incorporated if necessary before a layout is defined, thus improving the efficiency of a layout design process.
In still another embodiment, the second method may further includes, between the steps c) and d) and between the steps d) and e), the steps of: estimating, based on the pin allocation information, how long a wire length of the test data input or output circuit inserted will be after the circuit has been laid out; deciding whether or not a signal shaping buffer should be added to the test data input or output circuit to shape a waveform of a signal that has been rounded during the propagation thereof; and adding a result of the decision as signal shaping buffer information to the pin combination information. The step d) preferably includes inserting the signal shaping buffer into the test data input circuit based on the signal shaping buffer information. And the step e) preferably includes inserting the signal shaping buffer into the test data output circuit based on the signal shaping buffer information. In such an embodiment, a signal shaping buffer can be incorporated if necessary before a layout is defined, thus improving the efficiency of a layout design process.
In still another embodiment, the step a) preferably includes obtaining timing adjusting flip-flop information indicating whether or not a timing adjusting flip-flop should be added to the test data input or output circuit to prevent the integrated circuit from operating erroneously due to a considerable signal delay defined with respect to a clock period thereof. The step d) preferably includes inserting the timing adjusting flip-flop into the test data input circuit based on the timing adjusting flip-flop information. And the step e) preferably includes inserting the timing adjusting flip-flop into the test data output circuit based on the timing adjusting flip-flop information. In such an embodiment, a timing adjusting flip-flop can be incorporated if necessary before a layout is defined, thus improving the efficiency of a layout design process.
In still another embodiment, the second method may further include, between the steps c) and d) and between the steps d) and e), the steps of: estimating, based on the pin allocation information, how long a signal delay of the integrated circuit will be with respect to the clock period thereof after the integrated circuit has been laid out; deciding whether or not a timing adjusting flip-flop should be added to the test data input or output circuit to prevent the integrated circuit from operating erroneously due to the signal delay; and adding a result of the decision as timing adjusting flip-flop information to the pin combination information. The step d) preferably includes inserting the timing adjusting flip-flop into the test data input circuit based on the timing adjusting flip-flop information. And the step e) preferably includes inserting the timing adjusting flip-flop into the test data output circuit based on the timing adjusting flip-flop information. In such an embodiment, a timing adjusting flip-flop can be incorporated if necessary before a layout is defined, thus improving the efficiency of a layout design process.
A third exemplary inserting method according to the present invention is adapted to insert a test circuit into an integrated circuit, which is made up of a plurality of functional blocks interconnected, such that test data can be externally input to at least one of the functional blocks when the functional block is tested. The method includes the steps of: a) obtaining routing information by analyzing interconnection routes of the functional block based on information about the integrated circuit; and b) obtaining pin combination information including input and output pin connection information for the at least one functional block under test. The input pin connection information represents interconnection between an input pin of the functional block under test and an associated external test data input pin to be connected to the input pin. The output pin connection information represents interconnection between an output pin of the functional block under test and an associated external test data output pin to be connected to the output pin. The method further includes the step of c) inserting a test data input circuit and an input signal direction controller between the external test data input pin and the functional block under test. The test data input circuit is used for inputting test data through the external test data input pin to the input pin of the functional block under test in a test mode based on the pin combination information. The input signal direction controller is provided for enabling the external test data input pin, which functions as an output or bidirectional pin in a normal operation mode, to input the test data in the test mode. The method further includes the step of d) inserting a test data output circuit and an output signal direction controller between the functional block under test and the external test data output pin. The test data output circuit is used for outputting the test data to the external test data output pin through the output pin of the functional block under test in the test mode based on the pin combination information. The output signal direction controller is provided for enabling the external test data output pin, which functions as an input or bidirectional pin in the normal operation mode, to output the test data in the test mode. The method further includes the step of e) updating the routing information based on how the test data input or output circuit inserted is connected and outputting the updated routing information as testable integrated circuit information.
According to the third inserting method, the pin combination information including the input and output pin connection information, which represents which input or output pin of the functional block under test should be connected to each external test data input or output pin, can be created automatically based on the routing information of the integrated circuit. Thus, information about a testable integrated circuit including the test circuit can be obtained quickly without actually designing the test circuit to be inserted into the functional block under test. That is to say, routing information for testing the functional block can be created without performing a great deal of modification work manually. As a result, the number of design process steps can be further reduced. In addition, even if the external test data input pin functions as an output pin in the normal operation mode, the input pin can be used as a bidirectional pin by inserting the input signal direction controller thereto. Similarly, even if the external test data output pin functions as an input pin in the normal operation mode, the output pin can also be used as a bidirectional pin by inserting the output signal direction controller thereto. Thus, the inventive method is easily adaptable to an automated design process.
In one embodiment of the present invention, the step b) preferably includes estimating how long a signal delay of the integrated circuit will be with respect to a clock period after the integrated circuit has been laid out and then obtaining partitioning information for classifying each of the input and output pin connection information into a plurality of groups so as to reduce the signal delay in the normal mode. The step c) preferably includes inserting the test data input circuit into each said group based on the partitioning information. And the step d) preferably includes inserting the test data output circuit into each said group based on the partitioning information. In such an embodiment, the test circuits inserted can be laid out for the respective groups based on the positional relationship between the pins of the functional block and the external test data input and output pins laid out. As a result, efficiency of a layout design process can be improved.
In one embodiment of the present invention, the step b) preferably includes estimating how long a wire between adjacent ones of the functional blocks will be after the integrated circuit has been laid out and then obtaining the pin combination information so as to shorten a maximum or average wire length of the test data input and output circuits in the integrated circuit. In such an embodiment, it is possible to reduce the processing load of analyzing and modifying a signal delay on subsequent layout design process steps. As a result, efficiency of a layout design process can be improved.
In another embodiment of the present invention, the step b) preferably includes the steps of: estimating, based on the pin combination information, how long a wire length of the test data input or output circuit inserted will be after the integrated circuit has been laid out; deciding whether or not a signal shaping buffer should be added to the test data input or output circuit to shape a waveform of a signal that has been rounded during the propagation thereof; and defining a result of the decision as signal shaping buffer information. The step c) preferably includes inserting the signal shaping buffer into the test data input circuit based on the signal shaping buffer information. And the step d) preferably includes inserting the signal shaping buffer into the test data output circuit based on the signal shaping buffer information. In such an embodiment, a signal shaping buffer can be incorporated if necessary before a layout is defined, thus improving the efficiency of a layout design process.
In still another embodiment, the step b) preferably includes the steps of: estimating, based on the pin combination information, how long a signal delay of the integrated circuit will be with respect to the clock period thereof after the integrated circuit has been laid out; deciding whether or not a timing adjusting flip-flop should be added to the test data input or output circuit to prevent the integrated circuit from operating erroneously due to the signal delay; and defining a result of the decision as timing adjusting flip-flop information. The step c) preferably includes inserting the timing adjusting flip-flop into the test data input circuit based on the timing adjusting flip-flop information. And the step d) preferably includes inserting the timing adjusting flip-flop into the test data output circuit based on the timing adjusting flip-flop information. In such an embodiment, a timing adjusting flip-flop can be incorporated if necessary before a layout is defined, thus improving the efficiency of a layout design process.
A first exemplary converting method according to the present invention is adapted to convert block-by-block test data prepared for each of a plurality of functional blocks, which are interconnected together to form an integrated circuit, into test data of the type making the functional blocks in the integrated circuit externally testable. The method includes the step of a) obtaining pin allocation information including input and output pin connection information for the at least one of the functional blocks under test. The input pin connection information represents interconnection between an input pin of the functional block under test and an associated external test data input pin to be connected to the input pin. The output pin connection information represents interconnection between an output pin of the functional block under test and an associated external test data output pin to be connected to the output pin. The method further includes the steps of: b) obtaining machine-readable pin combination information by analyzing the pin allocation information; and c) converting the block-by-block test data into the test data for the integrated circuit based on the pin combination information.
According to the first converting method, the block-by-block test data prepared for each of the functional blocks is converted into test data making the integrated circuit testable based on the pin combination information obtained by the first inserting method of the present invention. Thus, test data of the type making the integrated circuit externally testable can be defined on the block-by-block basis. As a result, a test process can be carried out on a semiconductor integrated circuit made up of a plurality of functional blocks in a much shorter time.
A second exemplary converting method according to the present invention is adapted to convert block-by-block test data prepared for each of a plurality of functional-blocks, which are interconnected together to form an integrated circuit, into test data of the type making the functional blocks in the integrated circuit externally testable. The method includes the steps of: a) obtaining routing information by analyzing interconnection routes of the functional block based on information about the integrated circuit; and b) obtaining pin combination information including input and output pin connection information for at least one of the functional blocks under test. The input pin connection information represents interconnection between an input pin of the functional block under test and an associated external test data input pin to be connected to the input pin. The output pin connection information represents interconnection between an output pin of the functional block under test and an associated external test data output pin to be connected to the output pin. The method further includes the step of d) converting the block-by-block test data into the test data for the integrated circuit based on the pin combination information.
According to the second converting method, the block-by-block test data prepared for each of the functional blocks is converted into test data making the integrated circuit testable based on the pin combination information obtained by the second inserting method of the present invention. Thus, test data of the type making the integrated circuit externally testable can be defined quickly on the basis of the functional blocks included in the integrated circuit.